1. Field of Invention
The invention relates to a level shift circuit and a DC-DC buck converter controller for using the same, and more particularly relates to a level shift circuit with a power-saving function and a DC-DC buck converter controller for using the same.
2. Description of Related Art
In the conventional DC-DC buck converting circuit, a level shift circuit is required to adjust the signal level for correctly turn on and off the high-side transistor of an N-type MOSFET. However, the conventional current type level shift circuit has a large power consumption and leakage paths, and so is not suitable for light-load. On the other hand, the conventional pulse type level shift circuit has no problems of leakage paths and large power consumption, but the pulse type level shift circuit keeps levels of output signals thereof through a parasitic capacitance of a transistor. When a reference level of the level shift circuit flutters, it is easy to cause a logic state of the output signal of the level shift circuit to be changed. Thus, the anti-interference ability of the pulse type level shift circuit is very poor.
FIG. 1 is a schematic diagram of a conventional current type level shift circuit. A first logic low level VS1 and a first logic high level VP1 are two logic levels of a first logic family. A second logic low level VS2 and a second logic high level VP2 are two logic levels of a second logic family. The function of the level shift circuit is used to transforming a high logic level and a low logic level of one logic family, i.e., the first logic high level VP1 and the first logic low level VS1, into the other logic family, i.e. the second logic high level VP2 and the second logic low level VS2.
When a first input signal S is at the first logic high level VP1 and a second input signal R is at the first logic low level VS1, a transistor MN4 is turned on and a transistor MN5 is turned off. At this moment, a current of a current source Ib flows through the current mirror composed of transistors MN1 and MN2 to make a current mirrored flow through the transistors MP1, MN4 and MN2. A transistor MP2 also simultaneously mirrors the current of the transistor MP1 to make a level of a first output signal Q raise to the second logic high level VP2. Moreover, because the transistor MN5 is cut off and leads to no current, the transistors MP4 and MP3 are also cut off. Because the level of the first output signal Q is at the second logic high level VP2 and a transistor MN7 is turned on, a potential of a second output signal QN is reduced to the second logic low level VS2. Similarly, when the first input signal S is at the first logic low level VS1 and the second input signal R is at the first logic high level VP1, the level of the first output signal Q is at the second logic low level VS2 and the level of the second output signal ON is at the second logic high level VP2. According to the level shift mentioned above, the first input signal S and the second input signal R of the first logic high level VP1 and the first logic low level are transformed into the first output signal Q and the second output signal QN of the second logic high level VP2 and the second logic low level VS2.
For ensuring a transforming speed of the level shift, when the first input signal S is at a high level and the second signal R is at a low level, the current flowing from the second logic high level VP2 via the transistors MP1, MN4 and MN2 to the first logic low level VS1 is designed to be larger. Similarly, when the first input signal S is at a low level and the second input signal R is at a high level, the current flowing from the second logic high level VP2 via the transistors MP4, MN5 and MN3 to the first logic low level VS1 is also designed to be larger. This circuit design can ensure the transforming speed of the level shift in the current type level shift circuit. However, such circuit design has the higher power consumption. Especially, the DC-DC buck converting circuit operates under a light-load, such as the diode emulation mode. In this mode, the larger current continuously flowing through the current type level shift circuit is not conducive to power-saving. The second logic high level VP2 may be provided by an extra boost circuit, not provided by an independent voltage source. The larger current continuously flowing leads to the second logic high level VP2 falling down and so a voltage difference between the second high level VP2 and the second logic low level VS2 is decreased.
FIG. 2 is schematic diagram of a conventional improved current type level shift circuit. Compared with that shown in FIG. 1, the improved current type level shift circuit extra increases transistors MN8 and MN9. The main function of the transistors MN8 and MN9 is voltage suppression, and gate electrodes thereof are coupled to the first logic high level VP1 for ensuring source electrodes of the transistors MN8 and MN9, i.e., potentials of drain electrodes of the transistors MN4 and MN5 are clamped under the first logic high level VP1. Under this circuit design, both the transistors MN4 and MN5 can be low-voltage transistors, and it is conducive to raise the switching speed of the transistors MN4 and MN5. However, large power consumption problem still exists.
FIG. 3 is a schematic diagram of a conventional pulse type level shift circuit. Pulse signals VPS and VPR are pulse signals respectively triggered on rising-edges of the first input signal S and the second signal R, and have narrow pulse widths. The pulse signals VPS and VPR are respectively coupled to gate electrodes of transistors MN2 and MN3. FIG. 4 shows waveform diagrams of the pulse type level shift circuit shown in FIG. 3. When both the first input signal S and the pulse signal VPS are at the first logic high level VP1 and the second input signal R is at the first logic low level VS1, a large current flows from the second logic high level VP2 via the transistors MP1, MN4 and MN2 to the first logic low level VS1. The transistor MP2 mirrors a current of the transistor MP1 to make the first output signal Q raise to the second logic high level VP2, while the second output signal QN is at the second logic low level VS2. When the first input signal S is still at the first logic high level VP1 and the pulse signal VPS is changed to be at the first logic low level VS1, the current of the transistor MP1 is zero. At this moment, the whole level shift circuit does not consume any current. Similarly, when both the second input signal R and the pulse signal VPR are at the first logic high level VP1 and the first input signal S at is the first logic low level VS1, the large current flows from the second logic high level VP2 via the transistors MP4, MN5 and MN3 to the first logic low level VS1. The transistor MP3 mirrors the current of the transistor MP4 to make the second output signal QN raise to the second logic high level VP2, while the first output signal Q is at the second logic low level VS2. Soon after, when the second input signal R is still at the first logic high level VP1 and the pulse signal VPR is changed to be at the first logic low level VS1. At this moment, the whole level shift circuit does not consume any current.
Advantages of the pulse type level shift circuit are speeding up the translating speed of the level shift due to the large current flowing through the pulse type level shift circuit, and lowering power consumption due to no current consumption after level shift has completed. However, the pulse type level shift circuit still has defects. When both the pulse signals VPR and VPS are at the logic low level, the levels of the first output signal Q and the second output signal QN are kept by the parasitic capacitances of the transistors, which causes the pulse type level shift circuit has poor anti-noise ability.
FIG. 5 is a schematic diagram of a level shift circuit disclosed in U.S. Pat. No. 7,839,197 of RICHTEK Technology Corporation. The level shift circuit shown in FIG. 5 is designed with the advantages of the pulse type level shift circuit and the current type level shift circuit. FIG. 6 shows waveform diagrams of the pulse type level shift circuit shown in FIG. 5. When the first input signal S and the pulse signal VPS are at the first logic high level VP1 and the second input signal R is at the first logic low level VS1, a current flows from the second logic high level VP2 via the transistors M1, M5 and M11 and a basic current source 642 to the first logic low level VS1. At this moment, a transistor M8 mirrors a current of the transistor M1 to make the first output signal Q be at the second logic high level VP2 and the second output signal QN be at the second logic low level VS2. When the first input signal S is still at the first logic high level VP1 and the pulse signal VPS is changed to be at the first logic low level VS1, the transistor M111 is cut off and the basic current source 642 still maintains a small basic current flowing through the transistors M5 and M1, and the small current is used to maintain the first output signal Q to continuously be at the second logic high level VP2. Similarly, when the second input signal R and the pulse signal VPR are at the first logic high level VP1 and the first input signal S is at the first logic low level VS1, the current flows from the second logic high level VP2 via the transistors M4, M6 and M12 and a basic current source 644 to the first logic low level VS1. At this moment, a transistor M7 mirrors a current of the transistor M4 to make the second output signal QN be at the second logic high level VP2 and the first output signal Q become the second logic low level VS2. When the second input signal R is still at the first logic high level VP1 and the pulse signal VPR is changed to be at the first logic low level VS1, the transistor M12 is cut off and the basic current source 644 still maintains a small basic current flowing through the transistors M6 and M4, and the small current is used to maintain the second output signal QN to be continuously at the second logic high level VP2. The transistors M2 and M3 are two mirror acceleration transistors.
Advantages of the level shift circuit shown in FIG. 5 involves the advantage of the high speed level shift of the pulse type level shift circuit and the good anti-noise ability of the current type level shift circuit. FIG. 7 shows waveform diagrams of the second logic high level VP2 and the second logic low level VS2 of the level shift circuit shown in FIG. 5. In the continuous current mode, the converting circuit continuously operates to make the boost circuit retain the potential of the second logic high level VP2. However, in the diode emulation mode, the basic current sources 642 and 644 of the level shift circuit still provide the small current and continuously consumes the energy stored in the boost circuit, and it causes the voltage difference between the second logic high level VP2 and the second logic low level VS2 slowly dropping down and further is possible to cause the problem of the logic error level of the first output signal Q and the second output signal QN.